#ifndef BYTEREADC_REGISTERS_H
#define BYTEREADC_REGISTERS_H

#define BYTEREAD_BASE                  0x80000000

#define BYTEREAD_C0_DATA_ADDR            0x00

// Bit manipulation
#define MASK(_BITS)                     ((_BITS) == 32 ? -1U : (1U<<MIN((_BITS),31))-1)
#define PART_SELECT(_V,_LEFT,_RIGHT)    (((_V)>>(_RIGHT)) & MASK((_LEFT)-(_RIGHT)+1))
#define BIT_SELECT(_V,_BIT)             (((_V)>>(_BIT)) & 1)

// Control Bits
#define DMA_CONTROL_I(_R)         BIT_SELECT(_R,31)
#define DMA_CONTROL_TRAN_SIZE(_R) PART_SELECT(_R,11,0)

// Configuration bits
#define DMA_CONFIG_HALT(_R)       BIT_SELECT(_R,18)
#define DMA_CONFIG_ACT(_R)        BIT_SELECT(_R,17)
#define DMA_CONFIG_ITC(_R)        BIT_SELECT(_R,15)
#define DMA_CONFIG_ENA(_R)        BIT_SELECT(_R,0)

#endif
